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CDB43122
Evaluation Board for CS43122/CS4397
Features
l Demonstrates
Description
The CDB43122 evaluation board is an excellent means for quickly evaluating the CS43122 or CS4397 24bit192 kHz D/A converters. The board accepts SPDIF and SACD inputs and, with an analog output interface, presents line level signals via XLR connectors. Evaluation requires an analog signal analyzer and a digital signal source. The CS8414 digital audio receiver I.C. provides the system timing and data signals necessary to operate the Digital-to-Analog converter and will accept AES/EBU, SPDIF and EIAJ compatible audio data. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development in PCM and DSD modes. ORDERING INFORMATION CDB43122 Evaluation Board
recommended layout and grounding arrangements l CS8414 receives AES/EBU, S/PDIF, & EIAJ340 Compatible Digital Audio l Supports PCM Audio and SACD Audio l Requires only a digital signal source for a complete Digital-to-Analog Converter system l Included Wall Mount power supply
I
POWER SUPPLY REGULATION CS8414
ANALOG FILTER INPUT SELECTOR
CS43122
ANALOG FILTER
EXT. PCM/DSD
MODE SELECTOR
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2001 (All Rights Reserved)
MAR `01 DS526DB1 1
CDB43122
TABLE OF CONTENTS
1. CDB43122 SYSTEM OVERVIEW ............................................................................................. 3 2. CS43122 DIGITAL TO ANALOG CONVERTER ....................................................................... 3 3. CS8414A DIGITAL AUDIO RECEIVER .................................................................................... 3 4. EXTERNAL DIGITAL AUDIO DATA AND DSD INPUT PORT .................................................. 3 5. MODE CONTROL ..................................................................................................................... 3 6. AUTOMATIC SWITCHING MODE............................................................................................. 3 7. OUTPUT FILTER ....................................................................................................................... 4 8. POWER SUPPLIES .................................................................................................................. 4 9. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................. 4 10. CS43122 MODE SETTINGS..................................................................................................... 6 11. SCHEMATICS ......................................................................................................................... 7 12. PCB ARTWORK .................................................................................................................... 10
LIST OF FIGURES
Figure 1. Power Supply ................................................................................................................... 6 Figure 2. Output Filter ..................................................................................................................... 7 Figure 3. Input Reciever, DAC ........................................................................................................ 8 Figure 4. Silkscreen Top ................................................................................................................. 9 Figure 5. Top Layer ....................................................................................................................... 10 Figure 6. Second Layer ................................................................................................................. 11 Figure 7. Third Layer ..................................................................................................................... 12 Figure 8. Bottom Layer.................................................................................................................. 13
LIST OF TABLES
Table 1. Single Speed (16 to 50 kHz) Digital Interface Format Options.......................................... 5 Table 2. Single Speed (16 to 50 kHz) De-Emphasis Options ......................................................... 5 Table 3. Double Speed (50 to 100 kHz) Sample Rate Mode Options............................................. 5 Table 4. Quad Speed(100 to 200 kHz) Sample Rate Mode Options .............................................. 5 Table 5. 8x Interpolated Input Mode Options (CS43122 only) ........................................................ 5 Table 6. Direct Stream Digital Options (CS43122 only) ................................................................. 5 Table 7. SWITCH S2 MODE SETTINGS TABLE........................................................................... 6
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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CDB43122
1. CDB43122 SYSTEM OVERVIEW
HDCD PMD100 or PMD200. Notice that the board has provisions for terminating this input port for proper signal integrity using resistors R20 through R24. The board also features automatic mode switching between this port and the SPDIF port when used with a SACD player. See Section 6- "Automatic Mode Switching" for a complete description of this feature.
The CDB43122 evaluation board is an excellent means of quickly evaluating the CS43122 or CS4397 24 bit - 192 kHz audio D/A converters. The evaluation board features a CS8414 digital audio input interface receiver, an analog output buffer/filter, and on board power supply regulation to be used with a supplied AC Wall Mount power supply. The CS8414 provides an easy interface to 32 kHz to 96 kHz digital audio signal sources. The evaluation board also allows the user to supply external PCM data and DSD data through a 10-pin header for system development.
5. MODE CONTROL
The board utilizes a Dip Switch, "S2" to allow the user to select various operational modes of the CS43122 or CS4397. These modes include selection of the Digital Interface Format, De-emphasis, Sample Rate modes, Internal-External Digital Audio Data, PCM-DSD Automatic Switching, 64x 128x DSD Data, +3 V/+5 V Digital Supply voltage selection, and Mute control. See Tables 1 through 7 for a complete description of how the switch settings set the different operating modes of the CS43122.
2. CS43122 DIGITAL TO ANALOG CONVERTER
Please refer to the CS43122 or CS4397 product datasheets for a complete detailed description of these components.
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 1. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 datasheet.
6. AUTOMATIC MODE SWITCHING
The board features an automatic PCM or DSD input data switching mode for use with an external SACD player. When used with an external SACD player that has both a SPDIF output connected to J1 (U5) and DSD data output connected to the JP1 port, will allow the board to switch automatically between the two. Theory of operation - When an SACD player switches from playing a CD to a DSD disc, the SPDIF output data is disabled, the internal circuitry (U6, U2, U3, U4, U7) detects loss of an SPDIF source and automatically switches the Digital Data Input path (U8) to the DSD input port JP1. This feature can also be controlled from an external control signal by removing R60 and inputting a control signal into JP2. Logic low = PCM mode, Logic high = DSD mode.
4. EXTERNAL DIGITAL AUDIO DATA AND DSD INPUT PORT
The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, JP1. This header allows the evaluation board to accept externally generated clocks and data. The port is activated by setting the "MODE" Control Switch "S2" position 6 "INT/EXT" switch to the closed position. This port accepts PCM data, DSD (CS4397) data or data from an external 8X interpolator such as an
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CDB43122
7. OUTPUT FILTER
The output buffer/filter uses a balanced configuration. The balanced output filter consist of the 301 ohm resistors and the 2200pf capacitor, and is designed to cancel out the opposing multibit step pattern in each analog output to create a very low out of band noise spectrum. The op-amps provide output buffering and are configured to provide a +4.5db boost when the board switches into DSD mode to compensate for the 4.5db gain loss of the CS4397 in DSD mode. The balanced outputs are AC coupled and are provided on board by XLR type connectors. diodes D3 and D4 will clamp the input voltage. With JP5 connected, the +5V, VD and VA supplies will be regulated from the supplied +12V. To provide VA and VD externally via the designated binding posts, remove JP5 and lift pin 3 (bottom right pin) on VREG1; +5V to the CS8414 will still be provided by the on board regulator. WARNING: refer to the CS43122 datasheet for maximum allowable voltage levels. Operation outside this range can cause permanent damage to the device.
9. GROUNDING AND POWER SUPPLY DECOUPLING
For the user to be able to realize the high performance capabilities of the CS43122 or CS4397, it is recommended to pay careful attention to PC board layout, grounding, and placement of the power supply and decoupling capacitors. It is recommended when doing the PC board layout to use one ground plane underneath the part for both the analog and digital sections. Please review the attached PC board photo plots for an example of the suggested grounding method. It is also recommended to pay careful attention to the placement of the decoupling capacitors tied to VREF (pin 28). This pin requires a very low impedance path to ground at high frequencies as this pin draws high frequency current pulses at 6 MHz. It is important to place the .01 uf capacitor and 100 uf capacitor right next to the pin. Keep the connecting trace as short as possible. High performance capacitors such as NPO for the .01 uf and a low ESR electrolytic or tantalum for the 100 uf are recommended. Low frequency distortion (0-40Hz) performance can also be improved by increasing the FILT+ (pin 27) capacitance value up to 470uf.
8. POWER SUPPLIES
The CDB43122 comes supplied with an external 14 VAC Wall Mount power supply for convenience in setup, and to make measurements easier by eliminating ground loop problems between lab power supplies and measurement equipment (Note: the provided wall mount supply only operates at 110/120V and 50/60 Hz). The external 14 VAC voltage supplied at J11 is rectified, filtered and regulated to produce +/-12 volts by regulators U13 and U14. Separate voltage regulation is used for the digital control circuitry (CS8414) and for the digital power section and analog section for the CS43122 - CS4397. The digital power for the CS43122 - CS4397 is user selectable by switch #9 on dip switch S2. The open position sets the voltage regulator VREG2 to +5.0 volts, the closed position sets the voltage regulator to +3.3 volts. The CDB43122 evaluation board can also be powered by an external lab power supply by connecting +12 vdc to the +12V (J8) binding post, -12 vdc to 12V (J10), and ground to GND (J9). Up to +/- 13 volts is allowed before reverse voltage protection
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CDB43122
10. CS43122/CS4397 MODE SETTINGS (SW2)
Switch # 1 2 3 4 5 6 7 8 9 10 DEFAULT
Label MO M1 M2 M3 M4 INT/EX1 PCM/DSD 64/128X +3V/5V /MUTE CTL
Position Description OPEN = 1 See CS43122 datasheet for details OPEN = 1 See CS43122 datasheet for details OPEN = 1 See CS43122 datasheet for details OPEN = 1 See CS43122 datasheet for details OPEN = 1 See CS43122 datasheet for details OPEN = INT SETS THE INPUT MUX TO THE CS8414 (INT) OR TO JP1 (EX1) OPEN = DISABLED Activates Auto Switching for PCM and DSD OPEN = 128X SETS THE CLOCK MODE FOR DSD OPEN = +5V SETS THE DIGITAL POWER SUPPLY TO +3.3 OR +5 VOLTS OPEN = DISABLED ENABLES THE EXTERNAL MUTE CONTROL CIRCUITRY SWITCH 9 SET CLOSED, ALL OTHERS SET TO OPEN
SWITCH S2 MODE SETTINGS TABLE 1. Note: Switch #'s 1 to 4 must be open for audio mode to function properly.
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5
2
VOUT
VOUT 2
ADJ
VIN
ADJ
1N4003T J11 1 3 2 1 POWERJAC K 1
1
1
1
1
+12V 2 D6 1N4003T C55 4700UF 25V
1
2
3
1
2
3
D3 1 P6K E13 2
D4 1
-12 V
+5VA
1
VD+3/+ 5 +20V -12 V
P6K E13
C52 100UF 25V
C53 100UF 25V
C84 100UF 25V
C85 100UF 25V R62 953 1%
-20V +12V R64 110 1% R63 953 C59 10UF CSP_3 528 1% C56 47UF 25V R61 110 1%
-20V
C58 47UF 25V
C57 10UF CSP_3 528
VREG 2 LT1117 SO T223
JP5 +12V IN/EXT T
VREG 1 LT1117 SO T223
VREG 3 LT1117 SO T223
ADJ
OUT TAB IN
1 2
ADJ
OUT TAB IN
ADJ
+12V VD+3/+ 5
OUT TAB IN
1
2 4 3
1
2 4 3
1
+5.5V A R55 390 5% +3V/+ 5V R56 330 1% C46 47UF 25V R57 110 1% C49 10UF CSP_3 528 C50 10UF CSP_3 528 R59 365 RES_ 0805 1% R54 110 1% C47 10UF CSP_ 3528 R58 560 RES_ 0805 5% D2 GREEN LED POWE R C48 10UF CSP_3 528 R66 R65 330 110 C62 RES_0 80510UF 1% 1% CSP_3 528
2 4 3
+5V C60 10UF CSP_3 528 C61 10UF CSP_3 528
C51 47UF 25V
+3V/+ 5V
JMPHDR1
SHORTING-JUMPER JMPHDR2
VIN +12V
6
J8 +20V +12VDC GND -12VDC +5.5V A VD+3/+ 5 J9 J10 J12 J13 U14 LM 337T U13 LM 317T D5 C54 4700UF 25V
CDB43122
SHORTING-JUMPER
DS526DB1
Figure 1. Power Supply
0805 2 R37 AOUT_L EFTRN55 R91 N.S. PIH RN55 1% C30 2200PF DSD R81 R83 470 1 2SC3 326 Q7 2 3 432 C64 301 PIH 1% 3
7
C77 1UF CAP, 1UF, MF, 50V, 5%
.1UF -12 V 0805
R74 47K RES_0 805 1%
4 1 8
MUTE
RN55 MUT E
1 C27 8200PF JP2 CIRDIN_3-P MALE 2
R39 2SC3 326 Q2 1K RES_0 805 5%
R82
301 PIH 1% 1 RN55 2
RES_ 0805 1%
RES_0 805 5%
C65 .1UF +12V C78 0805 2 U15 LT1028 R43 ~ 6 RN55 C79 1UF CAP, 1UF, MF, 50V, 5% MUT E R75 47K RES_0 805 1% 1 R44 2SC3 326 1K Q3 RES_0 805 5% C35 8200PF 2 3 51 PIH 1% 7 10 UF 25V
3
R42 AOUT_ LEFT+
301 PIH 1% 3 RN55 C66
.1UF -12 V 0805
R84 R86 DSD RES_0 805 5% 470 1 2SC3 326 Q8 2 3
432
R85
RES_ 0805 1%
RN55 C67 .1UF +12V C80 0805 2 U17 LT1028 R48 ~ 6 RN55 C81 1UF CAP, 1UF, MF, 50V, 5% MUT E R76 47K RES_0 805 1% 1 R49 2SC3 326 1K Q4 RES_0 805 5% C40 8200PF 2 3 51 PIH 1% 7 10 UF 25V
R47 AOUT_RIGHT -
301 PIH 1% 3 RN55 C68 R92 N.S. PIH RN55 1% C43 2200PF R89 DSD RES_0 805 5% 470 1 2SC3 326 Q9 2 .1UF -12 V 0805
4 1 8
4 1 8
301 PIH 1%
3 JP3 CIRDIN_3-P MALE 1 2 C82 10 UF 25V R53 ~ 6 RN55 C83 1UF CAP, 1UF, MF, 50V, 5% MUT E R77 47K RES_0 805 1% 1 2SC3 326 R72 Q5 1K RES_0 805 5% C72 8200PF 2 3 51 PIH 1% 3 U19 LT1028
3
0805 2 R52 AOUT_RIGH T+ RN55 C71 301 PIH 1% 3
7
.1UF -12 V 0805
Figure 2. Output Filter 7
4 1 8
DS526DB1
R78 R80 DSD DSD RES_0 805 5% 470 1 2SC3 326 Q6 2 3
432
R79
301 PIH 1% RN55
RES_ 0805 1%
C63 .1UF +12V C76 U21 LT1028 R38 ~ 6 51 PIH 1% 10 UF 25V
R87
432
R88
301 PIH 1% RN55
RES_ 0805 1%
C69 .1UF +12V
CDB43122
OUT
1
.1UF 0805
+5V
5 3 5 3 5 3 5
1 2
SPDIF IN
R1 560 RES_0805 5% RESET PIN? U6 +5V JP6 C3 .1UF 0805 C2 .01UF 0805 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C ERR CD/F1 CE/F2 CC/F0 SDATA CB/E2 ERF CA/E1 M1 /C0/E0 M0 VDD VA+ DGND AGND RXP FILT RXN MCK FSYNC M2 SCK M3 CS12/FCK SEL U CBL 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D1 GREEN LED SPDIF ENABLED
CASE2 CASE1 GND2 GND1
.
.
.
.
.
.
.
(L=PCM) 2 R60 0 RES_0805 5%
-
+
.
.
.
1
1
1
1
U7 NC7SZ125 (L=ENABLE) PCM/DSD
6 5 4 2
.
1K INT/EXT 4 R2 RES_0805 5%
2
-
+
1K M1 4 R3 RES_0805 5% U2 NC7SZ125
2
-
+
1K M4 4 R4 RES_0805 5% U3 NC7SZ125
.
VCC
GND
VCC
GND
VCC
GND
VCC
GND
3
JP7
47UH
VD+3/+5 S1 PTS645TL50 DAC RESET 3 1
5 1 2
3
L2
VD+3/+5
3
1
.
.
1 R16 75 RES_0805 5% C8 .01UF 0805
CS8414-CS
VD+3/+5
R8 470 C4 .068UF RES_0805 0805 5% S2 1 2 3 4 VD+3/+5 5 6 7 8 9 /MUTE 10
R7 10K RES_0603 5% C7 .1UF 0805
R10 100 RES_0603 5% 4 2 +5.5VA
2
2
5
3
(L=PCM) U10 NC7SZ374 1 2 3 CP /OE GND VCC D Q C22 6 5 4 VD+3/+5 C21 .1UF 0805 INT/EXT R17 10K RES_0603 5% 2
5% 5% /MUTE C20 .1UF 0805 5% 1
.
.
VCC
GND
5
-
+
4
/INT/EXT
Q1 MMBT2907A L
3
2
5
0805 1 2 3 2
3 5
U11 IN2 GND IN1 SEL VCC OUT 6 5 4
(H=IN2) 64/128X INT/EXT 2 VD+3/+5
3
.
.
VCC
GND
GND
VCC
-
+
4
1 Q10 MMUN2111LT1
3
2
8
U5 TORX173 VCC 3 L1 47UH C1 VD+3/+5 VD+3/+5 VD+3/+5 VD+3/+5 +5V HDR1 SPDIF/DSD /INT/EXT 2 + 1K M3 4 R5 RES_0805 5% U4 NC7SZ125 +5.5VA PCM/DSD +5V D7 BAV99 PCM/DSD PCM/DSD R70 1.0K RES_0603 1% R71 499 RES_0603 1% R93 499 RES_0603 1% J1 C5 .1UF 0805 C6 10UF CSP_3528 20 19 18 17 16 15 14 13 12 11 (DEFAULT = OPEN) M0 M1 M2 M3 M4 INT/EXT PCM/DSD 64/128X +3V/+5V +3V/+5V /MUTE_CNTRL R6 10K RES_0603 5% R9 10K RES_0603 5% R11 10K RES_0603 5% R12 10K RES_0603 5% R13 10K RES_0603 5% R15 10K RES_0603 5% R18 10K RES_0603 5% VBIAS C74 10UF CSP_3528 (DSD CLK MODE) LOW = 256fs HIGH = 384fs JP1 2 4 6 8 10 1 3 5 7 9 SDATA LRCLK SCK MCLK DSD_R R19 N.S. RES_0805 5% Input Mux/Level Shifter 3 4 7 8 11 14 17 18 21 22 1 12 R23 N.S. 5% R24 N.S. 5% A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0-4 GND B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B5-9 VCC 2 5 6 9 10 15 16 19 20 23 13 24 VD+3/+5 R25 1K 5% R26 1K 5% R27 1K 5% R28 1K 5% C18 10UF C19 .01UF MCLK SCK LRCLK SDATA M1
ON
U1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 /RST M4 (AD0/CS) M3 (AD1/CDIN) M2 (SCL/CCLK) M0 (SDA/CDOUT) DGND1 VDD1 VDD2 DGND2 MCLK SCLK LR(CLK MODE) SDATA (DSD_L) M1 (DSD_R) VREF FILT + FILT CM OUT AOUT L AOUT L+ VA AGND1 AOUT R+ AOUT R AGND2 /MUTE C C/H /MUTE 28 27 26 25 24 23 22 21 20 19 18 17 16 15
C9 .01UF CSN_0603
100UFSMT C10 25V
C11 C12 .01UF 100UFSMT CSN_0603 25V
CM AOUT_LEFTAOUT_LEFT+ C13 .01UF C14 10UF CSP_3528
AOUT_RIGHT+ AOUT_RIGHT/MUTE_CNTRL +5.5VA
VD+3/+5
HDR5X2 R20 N.S. 5% R21 N.S. 5% R22 N.S. 5%
CS43122KS
L3 47UH S3 PTS645TL50 DAC MUTE VD+3/+5 +5.5VA
U8 QS3384 (L=CONNECT) VD+3/+5
C15 C16 .01UF 10UF CSP_3528
C17 .1UF 0805
R30 100 3 1 4 2
R29 10K
R31 10K
MUT E R33 10K RES_0603 5%
NC7SZ04
U9 +5V +5.5VA
.1UF VD+3/+5
- MODE TABLE AUTO SW ITCHING
PCM
DSD R90 10K RES_0603 5%
-12V
4
+
DSD = = = = = 1 0 1 1 0 M0 = 1 M1 = DSD_R M2 = 1 M3 = 0 M4 = 1 lrclk = 0 = 256fs lrclk = 1 = 384fs
NC7SZ157 U12 NC7SZ04 C23 .1UF 0805
NC7SZ04
U22
(H=
+4.5DB BOOST)
-12V
M0 M1 M2 M3 M4
CDB43122
DS526DB1
Figure 3. Input Receiver, DAC
CDB43122
Figure 4. Silkscreen Top
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CDB43122
Figure 5. Top Layer
10
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CDB43122
Figure 6. Second Layer
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11
CDB43122
Figure 7. Third Layer
12
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CDB43122
Figure 8. Bottom Layer
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